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Ordering number : EN*5190
CMOS LSI
LC651204N/F/L, LC651202N/F/L
4-Bit Single-Chip Microcontrollers for Small-Scale Control Applications
Preliminary Overview
The LC651204N/F/L and LC651202N/F/L are small-scale application microcontroller products in Sanyo's LC6500 series of 4-bit single-chip CMOS microcontrollers, and as such they fully support the basic architecture and instruction set of that series. These microcontrollers are provided in a 30-pin package and include 2 kilobytes (KB) and 4 KB of on-chip ROM. These products are appropriate for use in a wide range of applications, from applications that use a small number of controls and circuits that were previously implemented in standard logic to larger scale applications including audio equipment such as decks and players, office equipment, communications equipment, automotive equipment, and home appliances. Except for the lack of an A/D converter, these microcontrollers provide the same functionality as the LC651104, 02N/F/L. * Specification of the output level at reset: Can be specified to be high or low for ports C and D in port units. Interrupt functions -- Timer overflow vector interrupt (The interrupt state can be tested by the CPU.) -- Vector interrupts initiated by the INT pin or full/empty states of the serial I/O circuit. (The interrupt state can be tested by the CPU.) Stack levels: 8 levels (shared with interrupts) Timers: 4-bit prescaler plus 8-bit programmable timers Clock oscillator options to match application system specifications. -- Oscillator circuit options: 2-pin ceramic oscillator (N, F, and L versions) -- Divider circuit option: No divider, built-in divide-bythree circuit, built-in divide-by-four circuit (N and L versions) Supports continuous output of a square wave signal (with a period 64 times the cycle time) Watchdog timer -- RC time constant scheme -- A watchdog timer function can be allocated to one of the external pins as an option. EP version: LC65E1104, OTP version: LC65P1104
* * *
Features
* Fabricated in a CMOS process for low power (An instruction-controlled standby function is provided.) * ROM/RAM LC651204N/F/L - ROM: 4K x 8 bits, RAM: 256 x 4 bits LC651202N/F/L - ROM: 2K x 8 bits, RAM: 256 x 4 bits * Instruction set: The 80-instruction set provided by all members of the LC6500 series. * Wide operating power-supply voltage range of 2.5 to 5.5 volts (L version) * Instruction cycle time: 0.92 s (F version) * On-chip serial I/O circuit * Highly flexible I/O ports -- Number of ports: 6 ports with a total of 22 pins -- All ports: Can be used for both input and output I/O voltage: 15 V maximum (Only for C, D, E, and F ports with opendrain output specifications) Output current:20 mA maximum sink current (Capable of directly driving LEDs.) -- Options that allow specifications to be customized to match those of the application system. Specification of open-drain output or built-in pullup resistor: can be specified for all ports in bit units.
* *
*
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
93096HA (OT) No. 5190-1/35
LC651204N/F/L, LC651202N/F/L Package Dimensions unit : mm 3196-DIP30SD
[LC651204N/F/L, 651202N/F/L]
unit : mm 3073A-MFP30S
[LC651204N/F/L, 651202N/F/L]
SANYO: DIP30SD
SANYO: MFP30S
Note: The package drawings shown above are provided without error tolerances and are for reference purposes only. Contact Sanyo for official package drawings.
Function Overview
Item ROM RAM Instruction set Instruction Table reference Interrupts Timers Built-in functions Stack levels Standby function Number of ports Serial ports I/O voltage I/O ports Output current I/O circuit types Output levels at reset Square wave output Minimum cycle time Characteristics Power-supply voltage Power-supply current Oscillator Oscillator Other functions Divider circuit option Package LC651204N/1202N 4096 x 8 bits (1204N) 2048 x 8 bits (1202N) 256 x 4 bits (1204/1202N) 80 Supported 1 external, 1 internal 4-bit prescaler + 8-bit timer 8 Supports standby mode entered by the HALT instruction 22 I/O pins 4-bit or 8-bit I/O 15 V max. 10 mA typ. 20 mA max. LC651204F/1202F 4096 x 8 bits (1204F) 2048 x 8 bits (1202F) 256 x 4 bits (1204/1202F) 80 Supported 1 external, 1 internal 4-bit prescaler + 8-bit timer 8 Supports standby mode entered by the HALT instruction 22 I/O pins 4-bit or 8-bit I/O 15 V max. 10 mA typ. 20 mA max. LC651204L/1202L 4096 x 8 bits (1204L) 2048 x 8 bits (1202L) 256 x 4 bits (1204/1202L) 80 Supported 1 external, 1 internal 4-bit prescaler + 8-bit timer 8 Supports standby mode entered by the HALT instruction 22 I/O pins 4-bit or 8-bit I/O 15 V max. 10 mA typ. 20 mA max.
Memory
Open drain (n-channel) or built-in pull-up resistor output selectable on a per-bit basis. High or low can be selected in port units. (ports C and D only) Supported 2.77 s (VDD 3 V) 3 to 5.5 V 1.5 mA typ. Ceramic (800 kHz, 1 MHz, 4 MHz) 1/1, 1/3, 1/4 DIP30S-D MFP30S Supported 0.92 s (VDD 3 V) 3 to 5.5 V 2 mA typ. Ceramic (4 MHz) 1/1 DIP30S-D MFP30S Supported 3.84 s (VDD 2.5 V) 2.5 to 5.5 V 1.5 mA typ. Ceramic (800 kHz, 1 MHz, 4 MHz) 1/1, 1/3, 1/4 DIP30S-D MFP30S
Note: Sanyo will announce details on oscillator elements and oscillator circuit constants as recommended application circuits are developed. Customers should check with Sanyo for the latest information as the development process progresses.
No. 5190-2/35
LC651204N/F/L, LC651202N/F/L Pin Assignment Common assignments for the DIP and MFP packages
Note: NC pins must be connected to VSS.
Top view
Pin Functions
Pin OSC1, OSC2 RES PA0 to 3 PC0 to 3 PD0 to 3 PE0 to 1 PF0 to 3 PG0 to 3 TEST INT SI SO SCK NC WDR Function Connections for a ceramic oscillator element Reset I/O dual-function port A0 to A3 I/O dual-function port C0 to C3 I/O dual-function port D0 to D3 I/O dual-function port E0 to E1 I/O dual-function port F0 to F3 I/O dual-function port G0 to G3 Test Interrupt request Serial input Serial output Serial clock input and output No connection Watchdog reset
Note: The SI, SO, SCK, and INT pins are shared function pins that are also used as PF0 to PF3.
No. 5190-3/35
LC651204N/F/L, LC651202N/F/L System Block Diagram
RAM: Data memory F: Flag WR: Working register AC: Accumulator ALU: Arithmetic and logic unit DP: Data pointer E: E register CTL: Control register OSC: Oscillator circuit TM: Timer STS: Status register
ROM: Program memory PC: Program counter INT: Interrupt control IR: Instruction register I.DEC: Instruction decoder CF, CSF: Carry flag, carry save flag ZF, ZSF: Zero flag, zero save flag EXTF: External interrupt request flag TMF: Internal interrupt request flag
No. 5190-4/35
LC651204N/F/L, LC651202N/F/L Development Support Sanyo provides the following items to support application development using the LC651204 and LC651202. 1. User's manual The "LC651104/1102 User's Manual" is used with these microcontrollers. 2. Development tool manual See the "EVA800 - LC651104/1102 Development Tool Manual" for details on use of the EVA-800 system. 3. Development tool * Program development (using the EVA-800 system) -- MS-DOS host computer system *1 -- Cross assembler ... MS-DOS-based cross assembler: LC65S.EXE -- Evaluation chip: LC6595 -- Emulator: The EVA-800 main unit plus the evaluation chip * Program development (using the EVA-86000 system): Use the EVA86K-ECB651100. * Program evaluation The on-chip EPROM microcontroller
Development Support System EVA-800 System
Note: 1. MS-DOS is a registered trademark of Microsoft Corporation 2. Here, "EVA-800" is a generic term for several emulators. Suffixes (A, B, etc.) will be attached to the name as new versions are developed. Note that the EVA-800 emulator (i.e., the model with no suffix) is an old version and cannot be used.
No. 5190-5/35
LC651204N/F/L, LC651202N/F/L Pin Functions
Pin VDD VSS OSC1 Pin no. 1 1 I/O -- -- * System clock oscillator 1 Input Connect an external ceramic oscillator element to these pins * Leave OSC2 open if an external clock is supplied. (1) External clock (2) Two-pin ceramic oscillator (3) Divider circuit option 1. No divider circuit 2. Divide-by-three circuit 3. Divide-by-four circuit * I/O port A0 to A3 Input in 4-bit units using the IP instruction Output in 4-bit units using the OP instruction Port bits can be tested in bit units using the BP and BNP instructions. PA0 to PA3 4 I/O Port bits can be set or cleared in bit units using the SPB and RPB instructions. * PA3 is used for standby control. * Applications must be designed so that no chattering (e.g. switch bounce) occurs on the PA3 pin during a HALT instruction execution cycle. * I/O port C0 to C3 (1) Output open drain * High-level output * Low-level output (Depending on the option specified.) The same as PA0 to PA3. (1) Output open drain (2) Built-in pull-up resistor * Options (1) and (2) can be specified in bit units. High-level output (i.e., the output n-channel transistor will be off.) Open drain output select the options, connect to VSS. -- -- Power supply Function Options -- State at reset -- Handling when unused --
OSC2
1
Output
PC0 to PC3
4
I/O
The PC0 to PC3 pin functions are (2) Built-in pull-up resistor identical to those of the PA0 to 3 pins.* (3) High-level output at reset * High or low can be specified as the (4) Low-level output at reset output at reset as an option. * Options (1) and (2) can be Note: These pins do not have a specified in bit units. standby control function. * Option (3) and (4) are specified in 4-bit units. * I/O port D0 to D3 The same as PC0 to PC3.
PD0 to PD3
4
I/O
The PD0 to PD3 pin functions and options are identical to those of the PC0 to PC3 pins.
The same as PC0 to PC3.
The same as PA0 to PA3.
Continued on next page.
No. 5190-6/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Pin Pin no. I/O Function * I/O port E0 to E1 Input in 4-bit units using the IP instruction Output in 4-bit units using the OP instruction Port bits can be set or cleared in bit units using the SPB and RPB instructions. 2 I/O Port bits can be tested in bit units using the BP and BNP instructions. * The PE0 pin also has a continuous pulse (64*Tcyc) output function. * The PE1 pin can be set to function as the WDR watchdog timer reset pin as an option. Options (1) Output open drain (2) Built-in pull-up resistor * Options (1) and (2) can be specified in bit units. (3) Normal port PE1 (4) Watchdog timer reset WDR (5) (3) or (4) can be specified. State at reset High-level output (i.e., the output n-channel transistor will be off.) Handling when unused The same as PA0 to PA3.
PE0 to PE1 /WDR
* I/O port F0 to F3 This port has the same functions and options as PE0 to PE1. * * The pins PF0 to PF3 are also used as the serial interface and the INT pin. PF0/SI PF1/SO PF2/SCK PF3/INT 4 I/O The function used can be selected under program control. SI ******Serial input port SO*****Serial output port SCK **Serial clock input or output INT ****Interrupt request input Serial I/O can be switched between 4bit and 8-bit operation under program control. Note: This port does not provide a continuous pulse output function. * I/O port G0 to G3 PG0 to PG3 4 I/O This port has the same functions and options as PE0 to PE1. * Note: This port does not provide a continuous pulse output function. 2 * NC pin. This pin must be connected to VSS in the EP and OTP versions. * System reset input * Connect an external capacitor for the power up reset. * A low level must be applied for at least four clock cycles for the reset startup sequence to operate correctly. * LSI test pin 1 Input Must be connected to VSS.
The same as PA0 to PA3.
The same as PA0 to PA3. The serial port function is disabled. The interrupt source is INT.
The same as PA0 to PA3.
The same as PA0 to PA3.
The same as PA0 to PA3.
The same as PA0 to PA3.
NC
--
--
Connect to VSS.
RES
1
Input
--
--
--
TEST
--
--
Must be connected to VSS.
No. 5190-7/35
LC651204N/F/L, LC651202N/F/L Oscillator Circuit Options
Option Circuit Conditions and notes The OSC2 pin must be left open. External clock
Ceramic oscillator
Divider Options
Option Circuit Conditions and notes * Supports both oscillator options. * The oscillator frequency or the external clock frequency must not exceed 1444 kHz (LC651204N and LC651202N) No divider (1/1) * The oscillator frequency or the external clock frequency must not exceed 4330 kHz (LC651204F and LC651202F) * The oscillator frequency or the external clock frequency must not exceed 1040 kHz (LC651204L and LC651202L) * Supports both oscillator options. * The oscillator frequency or the external clock frequency must not exceed 4330 kHz Built-in divide-by-three circuit
* Supports both oscillator options. * The oscillator frequency or the external clock frequency must not exceed 4330 kHz Built-in divide-by-four circuit
Caution: The oscillator and divider options are summarized in the following tables. The information presented in those tables is crucial when using these products.
No. 5190-8/35
LC651204N/F/L, LC651202N/F/L Divider Options for the LC651204N/1202N, LC651204F/1202F, and LC651204L/1202L LC651204N, LC651202N
Circuit type Frequency 800 kHz 1 MHz Ceramic oscillator 4 MHz External clock generated by a two-terminal RC oscillator circuit Use of an external clock with the ceramic oscillator option selected 670 k to 1444 kHz 2000 k to 4330 kHz 2600 k to 4330 kHz Divider option (cycle time) 1/1 (5 s) 1/1 (4s) 1/3 (3s) 1/4 (4s) 1/1 (6 to 2.77 s) 1/3 (6 to 2.77 s) 1/4 (6 to 3.70 s) VDD range 3 to 5.5 V 3 to 5.5 V 3 to 5.5 V 3 to 5.5 V 3 to 5.5 V 3 to 5.5 V 3 to 5.5 V This frequency cannot be used with the 1/1 divider (i.e., no divider circuit) option. Notes
Driving the circuit with an external clock is not possible. To use external clock drive, specify the two-terminal RC oscillator option.
LC651204F, LC651202F
Circuit type Ceramic oscillator External clock generated by a two-terminal RC oscillator circuit Use of an external clock with the ceramic oscillator circuit Frequency 4 MHz 670 k to 4330 kHz Divider option (cycle time) 1/1 (1 s) 1/1 (6 to 0.92 s) VDD range 3 to 5.5 V 3 to 5.5 V Notes
Driving the circuit with an external clock is not possible. To use external clock drive, specify the two-terminal RC oscillator option.
LC651204L LC651202L
Circuit type Frequency 800 kHz 1 MHz Ceramic oscillator 4 MHz External clock generated by a two-terminal RC oscillator circuit Use of an external clock with the ceramic oscillator option selected 670 k to 1040 kHz 2000 k to 3120 kHz 2600 k to 4160 kHz 1/4 (4s) 1/1 (6 to 3.84 s) 1/3 (6 to 3.84 s) 1/4 (6 to 3.84 s) 2.5 to 5.5 V 2.5 to 5.5 V 2.5 to 5.5 V 2.5 to 5.5 V Divider option (cycle time) 1/1 (5 s) 1/1 (4s) VDD range 2.5 to 5.5 V 2.5 to 5.5 V This frequency cannot be used with the 1/1, 1/3 divider (i.e., no divider circuit) option. Notes
Driving the circuit with an external clock is not possible. To use external clock drive, specify the two-terminal RC oscillator option.
No. 5190-9/35
LC651204N/F/L, LC651202N/F/L Port C and D Output State at Reset Options The output levels at reset of the I/O ports C and D can be selected from the following two options, which are specified in 4-bit units.
Option High-level output at reset Low-level output at reset Conditions and notes Ports C and D in 4-bit units Ports C and D in 4-bit units
Port Output Circuit Type Option The output circuit types of the I/O ports can be selected from the following two options in bit units.
Option Circuit Conditions and notes Ports A, C, D, E, F, and G Open drain output
Pull-up resistor output
Watchdog Timer Reset Option Whether the PE1/WDR pin functions as the normal port PE1 or as the WDR watchdog timer reset pin can be selected as an option.
No. 5190-10/35
LC651204N/F/L, LC651202N/F/L LC651204N, 651202N Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Symbol Conditions VDD OSC2 OSC1 *1 TEST, RES PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PA0 to 3, PG0 to 3 I/O ports Average value per pin over a 100-ms period (1) Total current for pins PC0 to 3, PD0 to 3, and PE0 to 1*2 Total current for pins PF0 to 3, PG0 to 3, and PA0 to 3*2 I/O ports PC0 to PC3 PD0 to PD3 PE0 to PE1 PF0 to PF3 PG0 to PG3 PA0 to PA3 OD specification ports PU specification ports Applicable pins/notes Ratings -0.3 to +7.0 Voltages up to any generated voltage are allowed. -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to + 15 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -2 to +20 -2 to +20 -15 to +100 Unit V V V V V V V mA mA mA Maximum supply voltage VDD max Output voltage VO VI (1) VI (2) VIO (1) I/O voltage VIO (2) VIO (3) Peak output current IOP IOA I Average output current
OA
Input voltage
I Allowable power dissipation Operating temperature Storage temperature
OA
(2)
-15 to +100 250 150 -40 to +85 -55 to +125
mA mW mW C C
Pd max (1) Ta = -40 to +85C (DIP package) Pd max (2) Ta = -40 to +85C (MFP package) Topr Tstg
Allowable Operating Ranges at Ta = -40 to 85C, VSS = 0 V, VDD = 3.0 to 5.5 V (unless otherwise specified)
Parameter Operating power-supply voltage Standby power-supply voltage Symbol VDD VST VIH (1) VIH (2) VIH (3) Input high-level voltage VIH (4) VIH (5) VIH (6) VIH (7) RAM and register values retained *3 Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off VDD = 1.8 to 5.5 V External clock specifications Conditions VDD VDD OD specification ports C, D, E, and F PU specification ports C, D, E, and F Port A, G The INT, SCK, and SI pins with OD specifications The INT, SCK, and SI pins with PU specifications RES OSC1 Applicable pins/notes Ratings min 3.0 1.8 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD 0.8 VDD 0.8 VDD 0.8 VDD typ max 5.5 5.5 13.5 VDD VDD 13.5 VDD VDD VDD Unit V V V V V V V V V
Continued on next page.
No. 5190-11/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Parameter Symbol VIL (1) VIL (2) VIL (3) VIL (4) Input low-level voltage VIL (5) VIL (6) VIL (7) VIL (8) VIL (9) VIL (10) Operating frequency (cycle time) fop (Tcyc) Frequencies up to 4.33 MHz are supported if the divide-bythree or divide-by-four divider circuit option is used. Conditions Output n-channel transistor off Output n-channel transistor off Output n-channel transistor off Output n-channel transistor off External clock specifications External clock specifications VDD = 4 to 5.5 V VDD = 3 to 5.5 V VDD = 4 to 5.5 V VDD = 3 to 5.5 V VDD = 4 to 5.5 V VDD = 3 to 5.5 V VDD = 4 to 5.5 V VDD = 3 to 5.5 V VDD = 4 to 5.5 V VDD = 3 to 5.5 V Applicable pins/notes Port Port INT, SCk, SI INT, SCk, SI OSC1 OSC1 TEST TEST RES RES Ratings min VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS 670 (6) typ max 0.2VDD 0.2VDD 0.2VDD 0.2VDD 0.2VDD 0.2VDD 0.2VDD 0.2VDD 0.2VDD 0.2VDD 1444 (2.77) Unit V V V V V V V V V V kHz (s)
VDD = 3 to 5.5 V
External clock conditions text Frequency Pulse width Rise and fall times Guaranteed oscillator constants Ceramic oscillator
Figure 1. The divide-by-three or divide-by-four divider circuit textH, textL option must be used if the clock frequency exceeds textR, textF 1.444 MHz.
VDD = 3 to 5.5 V VDD = 3 to 5.5 V
OSC1 OSC1
670 69
4330
kHz ns
VDD = 3 to 5.5 V
OSC1 See Table 1.
50
ns
Figure 2
No. 5190-12/35
LC651204N/F/L, LC651202N/F/L Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 5.5 V (unless otherwise specified)
Parameter Symbol Conditions Output n-channel transistor off (Includes the n-channel transistor off leakage current.) VIN = 13.5 V Output n-channel transistor off (Includes the n-channel transistor off leakage current.) VIN = VDD External clock mode, VIN = VDD Output n-channel transistor off VIN = VSS Output n-channel transistor off VIN = VSS VIN = VSS External clock mode, VIN = VSS IOH = -50 A VDD = 4.0 to 5.5 V IOH = -10 A VDD = 3.0 to 5.5 V IOL = 10 mA, VDD = 4.0 to 5.5 V IOL = 1 mA, with the IOL for all ports no more than 1 mA. VDD = 3.0 to 5.5 V Applicable pins/notes Ports C, D, E, and F with open-drain specifications Ports A and G with open-drain specifications OSC1 Ports with open-drain specifications Ports with pull-up resistor specifications RES OSC1 -1.0 -1.3 -45 -1.0 -0.35 -10 Ratings min typ max 5.0 Unit A
IIH (1) Input high-level current IIH (2) IIH (3) IIL (1) Input low-level current IIL (2) IIL (3) IIL (4) VOH (1) Output high-level voltage VOH (2) VOL (1) Output low-level voltage Schmitt characteristics Hysteresis voltage High-level threshold voltage Low-level threshold voltage VOL (2) VHIS VtH VtL IDDOP (1) IDDOP (2) IDDOP (3) External clock IDDOP (4)
1.0 1.0
A A A mA A A V V
Ports with pull-up V -1.2 resistor specifications DD Ports with pull-up V -0.5 resistor specifications DD Port Port 0.1 VDD RES, INT, SCK, 0.4 VDD and SI OSC1 with Schmitt specifications 0.2 VDD *4 0.8 VDD 0.6 VDD 1.5 1.5 1.5 1.5 0.05 0.025 5 4 4 5 10 5 1.5 0.5
V V V V V
Current drain Ceramic oscillator
Operating, output n-channel transistors off, Ports = VDD Figure 2, 4 MHz, divide-by-three circuit Figure 2, 4 MHz, divide-by-four circuit Figure 2, 800 kHz 670 to 1444 kHz, no divider circuit 2000 to 4330 kHz, divide-by-three circuit 2600 to 4330 kHz, divide-by-four circuit Output n-channel transistor off, VDD = 5.5 V Ports = VDD, VDD = 3 V
VDD VDD VDD VDD VDD VDD
mA mA mA mA A A
Standby mode
IDDst
Continued on next page.
No. 5190-13/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Parameter Oscillator characteristics Ceramic oscillator Oscillator frequency fCFOSC *5 Figure 2, fo = 800 kHz Figure 2, fo = 1 MHz Figure 2, fo = 4 MHz, divide-by-three or divide-by-four circuit Figure 3, fo = 800 kHz, 1 MHz, 4 MHz Divide-by-three or divide-by-four circuit Output n-channel transistor off Vin = VSS, VDD = 5 V Vin = VSS, VDD = 5 V Ports with pull-up resistor specifications RES 8 100 14 250 OSC1, OSC2 OSC1, OSC2 OSC1, OSC2 768 960 3840 800 1000 4000 832 1040 4160 kHz kHz kHz Symbol Conditions Applicable pins/notes Ratings min typ max Unit
Oscillator stabilization time Pull-up resistors I/O ports RES External reset characteristics Reset time
tCFS RPP Ru
5
ms
30 400
k k
tRST Cp f = 1 MHz With all pins other than the pin being measured at VIN = VSS Figure 5 Figure 5 Figure 5 Figure 5 Figure 5 Figure 5 SCK SCK SCK SCK SCK SCK 1.0 1.0 3.0
See Figure 4. 10 pF
Pin capacitance Serial clock Input clock cycle time Output clock cycle time Input clock low-level pulse width Output clock low-level pulse width Input clock high-level pulse width Output clock high-level pulse width
tCKCY (1) tCKCY (2) tCKL (1) tCKL (2) tCKH (1) tCKH (2)
s 64xTCYC *6 s s 32xTCYC s s 32xTCYC s
Continued on next page.
No. 5190-14/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Parameter Serial input Data setup time Data hold time Serial output Stipulated with respect to the falling edge of SCK. For n-channel open-drain outputs only: External resistance: 1 k, external capacitance: 50 pF Figure 5 tICK tCKI Stipulated with respect to the rising edge of SCK. Figure 5 SI SI 0.4 0.4 s s Symbol Conditions Applicable pins/notes Ratings min typ max Unit
VDD (v)
Output delay time
tCKO
SO
0.6
s
Pulse output Period High-level pulse width Low-level pulse width
tPCY tPH tPL CW
Figure 6 Tcyc = 4 x the system clock period For n-channel open-drain outputs only: External resistance: 1 k, external capacitance: 50 pF When PE1 has open-drain output specifications When PE1 has open-drain output specifications When PE1 has open-drain output specifications See Figure 7. See Figure 7. When PE1 has open-drain output specifications When PE1 has open-drain output specifications When PE1 has open-drain output specifications See Figure 7. See Figure 7. 4 to 5.5 3 to 5.5
PE0 PE0 PE0 WDR WDR WDR WDR WDR WDR WDR WDR WDR WDR 40 15 100 29
64 x TCYC 32 x TCYC 10% 32 x TCYC 10% 0.15% 6801% 1001%
s s s F k s ms
Guaranteed constants *7
RW Rl
Watchdog timer
Clear time (discharge) tWCT Clear period (charge) tWCCY CW Guaranteed constants *7 RW Rl Clear time (discharge) tWCT Clear period (charge) tWCCY
0.0475% 6801% 1001%
F k s ms
Note: 1. When driven internally using the oscillator circuit shown in Figure 3 with guaranteed constants, values up to the amplitude of the generated oscillation are allowed. 2. The average over a 100-ms period 3. The operating power-supply voltage VDD must be maintained from the point where a HALT instruction is executed until the point where the device has fully entered the standby state. Also, applications must be designed so that no chattering (e.g. switch bounce) occurs on the PA3 pin during a HALT instruction execution cycle. 4. When external clock is selected as the oscillator option, the OSC1 pin has Schmitt characteristics. 5. The values shown for fCFOSC are the frequencies for which oscillation is possible. The center frequency when a ceramic oscillator is used may differ by about 1% from the nominal value listed by the manufacturer of the ceramic oscillator element. See the specifications of the ceramic oscillator element for details. 6. Tcyc = 4 x the system clock period 7. If this device is used in an environment subject to condensation, extra care is required concerning leakage between PE1 and adjacent pins and leakage associated with external capacitors.
No. 5190-15/35
LC651204N/F/L, LC651202N/F/L
Figure 1 External Clock Input Waveform
Figure 2 Ceramic Oscillator Circuit
No. 5190-16/35
LC651204N/F/L, LC651202N/F/L
Figure 3 Oscillator Stabilization Period
Table 1: Guaranteed Ceramic Oscillator Constants
4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG CST4.00MGW (built-in capacitor version) 4 MHz (Kyocera Corporation) KBR4.0MSA KBR4.0MKS (built-in capacitor version) C1 C2 R C1 C2 R C1 1 MHz (Murata Mfg. Co., Ltd.) CSB1000J C2 R C1 1 MHz (Kyocera Corporation) KBR1000F C2 R C1 800 kHz (Murata Mfg. Co., Ltd.) CSB800J C2 R C1 800 kHz (Kyocera Corporation) KBR800F C2 R 33 pF 10% 33 pF 10% 0 33 pF 10% 33 pF 10% 0 100 pF 10% 100 pF 10% 2.2 k 100 pF 10% 100 pF 10% 0 100 pF 10% 100 pF 10% 2.2 k 220 pF 10% 220 pF 10% 0 Note: When the power supply rise time is zero, the reset time with CRES = 0.1 F will be between 5 and 50 ms. If the power supply rise time is comparatively long, increase the value of CRES so that the reset time is over 5 ms.
Figure 4 Reset Circuit
No. 5190-17/35
LC651204N/F/L, LC651202N/F/L
Figure 5 Serial I/O Timing
With load conditions identical to those shown in Figure 5
Figure 6 Port PE0 Pulse Output Timing
tWCCY: Charge time due to the external components CW, RW, and Rl. tWCT: Discharge time due to program processing
Figure 7 Watchdog Timer Waveform
No. 5190-18/35
LC651204N/F/L, LC651202N/F/L LC651204F, 651202F Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Symbol Conditions VDD OSC2 OSC1 *1 TEST, RES PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PA0 to 3, PG0 to 3 I/O ports Average value per pin over a 100-ms period Total current for pins PC0 to 3, PD0 to 3, and PE0 to 1 *2 Total current for pins PF0 to 3, PG0 to 3, and PA0 to 3*2 I/O ports PC0 to 3 PD0 to 3 PE0 to 1 PF0 to 3 PG0 to 3 PA0 to 3 OD specification ports PU specification ports Applicable pins/notes Ratings -0.3 to +7.0 Voltages up to any generated voltage are allowed. -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to + 15 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -2 to +20 -2 to +20 -15 to +100 Unit V V V V V V V mA mA mA Maximum supply voltage VDD max Output voltage VO VI (1) VI (2) VIO (1) I/O voltage VIO (2) VIO (3) Peak output current IOP IOA IOA (1) Average output current IOA (2) Allowable power dissipation Operating temperature Storage temperature
Input voltage
-15 to +100 250 150 -40 to +85 -55 to +125
mA mW mW C C
Pd max (1) Ta = -40 to +85C (DIP package) Pd max (2) Ta = -40 to +85C (MFP package) Topr Tstg
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 5.5 V (unless otherwise specified)
Parameter Operating power-supply voltage Standby power-supply voltage Symbol VDD VST VIH (1) VIH (2) VIH (3) Input high-level voltage VIH (4) VIH (5) VIH (6) VIH (7) VIL (1) VIL (2) Input low-level voltage VIL (3) VIL (4) VIL (5) RAM and register values retained *3 Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off VDD = 1.8 to 5.5 V External clock specifications Output n-channel transistors off Output n-channel transistors off External clock specifications Conditions VDD VDD OD specification ports C, D, E, and F PU specification ports C, D, E, and F Port A, G The INT, SCK, and SI pins with OD specifications The INT, SCK, and SI pins with PU specifications RES OSC1 Port INT, SCK, SI OSC1 TEST RES Applicable pins/notes Ratings min 3.0 1.8 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD 0.8 VDD 0.8 VDD 0.8 VDD VSS VSS VSS VSS VSS typ max 5.5 5.5 13.5 VDD VDD 13.5 VDD VDD VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD Unit V V V V V V V V V V V V V V
Continued on next page.
No. 5190-19/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Parameter Operating frequency (cycle time) External clock conditions Frequency Pulse width Rise and fall times Guaranteed oscillator constants Ceramic oscillator text textH, textL Figure 1 textR, textF Figure 2 OSC1 OSC1 OSC1 See table 1. 670 69 50 4330 kHz ns ns Symbol fop (T cyc) Conditions Applicable pins/notes Ratings min 670 (6) typ max 4330 (0.97) Unit kHz (s)
Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 3.0 to 5.5 V (unless otherwise specified)
Parameter Symbol Conditions Output n-channel transistor off (Includes the n-channel transistor off leakage current.) VIN = 13.5 V Output n-channel transistor off (Includes the n-channel transistor off leakage current.) VIN = VDD External clock mode, VIN = VDD Output n-channel transistor off VIN = VSS Output n-channel transistor off VIN = VSS VIN = VSS External clock mode, VIN = VSS IOH = -50 A IOH = -10 A IOL = 10 mA IOL = 1 mA, with the IOL for all ports no more than 1 mA. 0.1 VDD RES, INT, SCK, 0.4 VDD and SI OSC1 with Schmitt specifications *4 0.25VDD Figure 2, 4 MHz 670 to 1444 kHz *1 Operating, output n-channel transistors off, Ports = VDD Output n-channel transistor off, VDD = 5.5 V Ports = VDD VDD = 3 V VDD 2 0.8 VDD 0.6 VDD 6 V V V mA Applicable pins/notes Ports C, D, E, and F with open-drain specifications Ports A and G with open-drain specifications OSC1 Ports with open-drain specifications Ports with pull-up resistor specifications RES OSC1 -1.0 -1.3 -45 -1.0 -0.35 -10 Ratings min typ max 5.0 Unit A
IIH (1) Input high-level current IIH (2) IIH (3) IIL (1) Input low-level current IIL (2) IIL (3) IIL (4) VOH (1) Output high-level voltage VOH (2) VOL (1) Output low-level voltage Schmitt characteristics VOL (2) VHIS VtH VtL IDDOP (1)
1.0 1.0
A A A mA A A V V
Ports with pull-up V -1.2 resistor specifications DD Ports with pull-up V -0.5 resistor specifications DD Port Port 1.5 0.5
V V
Hysteresis voltage High-level threshold voltage Low-level threshold voltage
Current drain Ceramic oscillator External clock
IDDOP (2)
VDD VDD VDD
2 0.05 0.025
6 10 5
mA A A
Standby mode
IDDst
Continued on next page.
No. 5190-20/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Parameter Oscillator characteristics Ceramic oscillator Oscillator frequency Oscillator stabilization time Pull-up resistors I/O ports RES External reset characteristics Reset time tRST f = 1 MHz With all pins other than the pin being measured at VIN = VSS Figure 5 Figure 5 Figure 5 Figure 5 Figure 5 Figure 5 Stipulated with respect to the rising edge of SCK. Figure 5 SCK SCK SCK SCK SCK SCK SI SI 0.2 0.2 0.4 64 x TCYC 32 x TCYC 10% 32 x TCYC 10% 0.6 32 x TCYC 0.6 32 x TCYC 2.0 64 x TCYC *6 See Figure 4. 10 pF RPP Ru fCFOSC tCFS Figure 2, fo = 4 MHz *5 Figure 3, fo = 4 MHz Output n-channel transistor off Vin = VSS, VDD = 5 V Vin = VSS, VDD = 5 V Ports with pull-up resistor specifications RES 8 100 14 250 30 400 k k OSC1, OSC2 3840 4000 4160 5 kHz ms Symbol Conditions Applicable pins/notes Ratings min typ max Unit
Pin capacitance Serial clock Input clock cycle time Output clock cycle time Input clock low-level pulse width Output clock low-level pulse width Input clock high-level pulse width Output clock high-level pulse width Serial input Data setup time Data hold time Serial output Output delay time Pulse output Period High-level pulse width
Cp
tCKCY (1) tCKCY (2) tCKL (1) tCKL (2) tCKH (1) tCKH (2) tICK tCKI tCKO tPCY
s s s s s s s s s
Stipulated with respect to the falling edge of SCK. For n-channel open-drain outputs only. External SO resistance: 1 k, external capacitance: 50 pF. Figure 5 Figure 6 Tcyc = 4 x the system clock period For n-channel open-drain outputs only: External resistance: 1 k, external capacitance: 50 pF PE0
s
tPH
PE0
s
Low-level pulse width
tPL
PE0
s
Continued on next page.
No. 5190-21/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Parameter Symbol CW Guaranteed constants *7 RW Rl Watchdog timer Clear time (discharge) tWCT Clear period (charge) tWCCY CW Guaranteed constants *7 RW Rl Clear time (discharge) tWCT Clear period (charge) tWCCY Conditions When PE1 has open-drain output specifications When PE1 has open-drain output specifications When PE1 has open-drain output specifications See Figure 7. See Figure 7. When PE1 has open-drain output specifications When PE1 has open-drain output specifications When PE1 has open-drain output specifications See Figure 7. See Figure 7. 4.5 to 5.5 Applicable pins/notes WDR WDR 3 to 5.5 WDR WDR WDR WDR WDR WDR WDR WDR 10 3.3 10 3.0 0.015% 6801% 1001% 1001% s ms F k s ms Ratings min typ 0.015% 6801% max Unit F k
VDD (v)
Note: 1. When driven internally using the oscillator circuit shown in Figure 2 with guaranteed constants, values up to the amplitude of the generated oscillation are allowed. 2. The average over a 100-ms period 3. The operating power-supply voltage VDD must be maintained from the point where a HALT instruction is executed until the point where the device has fully entered the standby state. Also, applications must be designed so that no chattering (e.g. switch bounce) occurs on the PA3 pin during a HALT instruction execution cycle. 4. When external clock is selected as the oscillator option, the OSC1 pin has Schmitt characteristics. 5. The values shown for fCFOSC are the frequencies for which oscillation is possible. 6. Tcyc = 4 x the system clock period 7. If this device is used in an environment subject to condensation, extra care is required concerning leakage between PE1 and adjacent pins and leakage associated with external capacitors.
No. 5190-22/35
LC651204N/F/L, LC651202N/F/L
Figure 1 External Clock Input Waveform
Figure 2 Ceramic Oscillator Circuit
Figure 3 Oscillator Stabilization Period
Table 1: Guaranteed Ceramic Oscillator Constants
4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MG CST4.00MGW (built-in capacitor version) 4 MHz (Kyocera Corporation) KBR4.0MSA KBR4.0MKS (built-in capacitor version) C1 C2 R C1 C2 R 33 pF 10% 33 pF 10% 0 33 pF 10% 33 pF 10% 0
Figure 4 Reset Circuit
Note: When the power supply rise time is zero, the reset time with CRES = 0.1 F will be between 5 and 50 ms. If the power supply rise time is comparatively long, increase the value of CRES so that the reset time is over 5 ms.
No. 5190-23/35
LC651204N/F/L, LC651202N/F/L
Figure 5 Serial I/O Timing
With load conditions identical to those shown in Figure 5
Figure 6 Port PE0 Pulse Output Timing
tWCCY: Charge time due to the external components CW, RW, and Rl. tWCT: Discharge time due to program processing
Figure 7 Watchdog Timer Waveform
No. 5190-24/35
LC651204N/F/L, LC651202N/F/L LC651204L, 651202L Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Symbol Conditions VDD OSC2 OSC1*1 TEST, RES PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PC0 to 3, PD0 to 3, PE0, 1, PF0 to 3 PA0 to 3, PG0 to 3 I/O ports Average value per pin over a 100-ms period Total current for pins PC0 to 3, PD0 to 3, and PE0 to 1 *2 Total current for pins PF0 to 3, PG0 to 3, and PA0 to 3 *2 I/O ports PC0 to 3 PD0 to 3 PE0 to 1 PF0 to 3 PG0 to 3 PA0 to 3 OD specification ports PU specification ports Applicable pins/notes Ratings -0.3 to +7.0 Voltages up to any generated voltage are allowed. -0.3 to VDD +0.3 -0.3 to VDD +0.3 -0.3 to + 15 -0.3 to VDD +0.3 -0.3 to VDD +0.3 -2 to +20 -2 to +20 -15 to +100 Unit V V V V V V V mA mA mA Maximum supply voltage VDD max Output voltage VO VI (1) VI (2) VIO (1) I/O voltage VIO (2) VIO (3) Peak output current IOP IOA IOA (1) Average output current IOA (2) Allowable power dissipation Operating temperature Storage temperature
Input voltage
-15 to +100 250 150 -40 to +85 -55 to +125
mA mW mW C C
Pd max (1) Ta = -40 to +85C (DIP package) Pd max (2) Ta = -40 to +85C (MFP package) Topr Tstg
Allowable Operating Ranges at Ta = -40 to +85C, VSS = 0 V, VDD = 2.5 to 5.5 V (unless otherwise specified)
Parameter Operating power-supply voltage Standby power-supply voltage Symbol VDD VST VIH (1) VIH (2) VIH (3) Input high-level voltage VIH (4) VIH (5) VIH (6) VIH (7) VIL (1) VIL (2) Input low-level voltage VIL (3) VIL (4) VIL (5) RAM and register values retained *3 Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off Output n-channel transistors off VDD = 1.8 to 5.5 V External clock specifications Output n-channel transistors off Output n-channel transistors off External clock specifications Conditions VDD VDD OD specification ports C, D, E, and F PU specification ports C, D, E, and F Port A, G The INT, SCK, and SI pins with OD specifications The INT, SCK, and SI pins with PU specifications RES OSC1 Port INT, SCK, SI OSC1 TEST RES Applicable pins/notes Ratings min 2.5 1.8 0.7 VDD 0.7 VDD 0.7 VDD 0.8 VDD 0.8 VDD 0.8 VDD 0.8 VDD VSS VSS VSS VSS VSS typ max 5.5 5.5 13.5 VDD VDD 13.5 VDD VDD VDD 0.2 VDD 0.15 VDD 0.15 VDD 0.2 VDD 0.15 VDD Unit V V V V V V V V V V V V V V
No. 5190-25/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Parameter Operating frequency (cycle time) Symbol fop (Tcyc) Conditions Frequencies up to 4.16 MHz are supported if the divide-by-four divider circuit option is used. OSC1 OSC1 OSC1 Applicable pins/notes Ratings min 670 (6) 670 150 typ max 1040 (3.84) 4160 100 See table 1. Unit kHz (s) kHz ns ns
External clock conditions Figure 1. The divide-by- three or divide-by-four Frequency text divider circuit option must be used if the clock Pulse width textH, textL frequency exceeds 1.040 MHz. Rise and fall times textR, textF Guaranteed oscillator constants Ceramic oscillator Figure 2
Electrical Characteristics at Ta = -40 to +85C, VSS = 0 V, VDD = 2.5 to 5.5 V (unless otherwise specified)
Parameter Symbol Conditions Output n-channel transistor off (Includes the n-channel transistor off leakage current.) VIN = 13.5 V Output n-channel transistor off (Includes the n-channel transistor off leakage current.) VIN = VDD External clock mode, VIN = VDD Output n-channel transistor off VIN = VSS Output n-channel transistor off VIN = VSS VIN = VSS External clock mode, VIN = VSS IOH = -10 A IOL = 3 mA IOL = 1 mA, with the IOL for all ports no more than 1 mA. Applicable pins/notes Ports C, D, E, and F with open drain specifications Ports A and G with open drain specifications OSC1 Ports with open drain specifications Ports with pull-up resistor specifications RES OSC1 -1.0 -1.3 -45 -1.0 -0.35 -10 Ratings min typ max 5.0 Unit A
IIH (1) Input high-level current IIH (2) IIH (3) IIL (1) Input low-level current IIL (2) IIL (3) IIL (4) Output high-level voltage VOH (1) VOL (1) Output low-level voltage Schmitt characteristics Hysteresis voltage High-level threshold voltage Low-level threshold voltage VOL (2) VHIS VtH VtL
1.0 1.0
A A A mA A A V
Ports with pull-up V -0.5 resistor specifications DD Port Port 0.1 VDD RES, INT, SCK, 0.4 VDD and SI OSC1 with Schmitt specifications *4 0.2 VDD 0.8 VDD 0.6 VDD 1.5 0.4
V V V V V
Continued on next page.
No. 5190-26/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Parameter Current drain IDDOP (1) Ceramic oscillator IDDOP (2) IDDOP (3) External clock IDDOP (4) Symbol Conditions Operating, output n-channel transistors off, Ports = VDD Figure 2, 4 MHz, divide-by-four circuit Figure 2, 4 MHz, divide-by-four circuit VDD = 2.5 V Figure 2, 800 kHz 670 to 1024 kHz, no divider circuit 2000 to 3120 kHz, divide-by-three circuit 2600 to 4160 kHz, divide-by-four circuit Output n-channel transistor off, VDD = 5.5 V Ports = VDD VDD = 2.5 V Applicable pins/notes Ratings min typ 1.5 0.5 1.5 1.5 0.05 0.020 max 4 1 4.0 4 10 4 Unit mA mA mA mA A A
VDD VDD VDD VDD VDD VDD
Standby mode Oscillator characteristics Ceramic oscillator Oscillator frequency
IDDst
fCFOSC *5
Figure 2, fo = 800 kHz Figure 2, fo = 1 MHz Figure 2, fo = 4 MHz, divide-by-four circuit Figure 3, fo = 800 kHz, 1 MHz, 4 MHz, divide-by-four circuit Output n-channel transistor off Vin = VSS, VDD = 5 V Vin = VSS, VDD = 5 V
OSC1, OSC2 OSC1, OSC2 OSC1, OSC2
768 960 3840
800 1000 4000
832 1040 4160 5
kHz kHz kHz ms
Oscillator stabilization time Pull-up resistors I/O ports RES External reset characteristics Reset time
tCFS RPP Ru
Ports with pull-up resistor specifications RES
8 100
14 250
30 400
k k
tRST f = 1 MHz With all pins other than the pin being measured at VIN = VSS
See Figure 4.
Pin capacitance
Cp
10
pF
Continued on next page.
No. 5190-27/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Parameter Serial clock Input clock cycle time Output clock cycle time Input clock low-level pulse width Output clock low-level pulse width Input clock high-level pulse width Output clock high-level pulse width Serial input Data setup time Data hold time Serial output Output delay time tCKO tICK tCKI Stipulated with respect to the rising edge of SCK. Figure 5 Stipulated with respect to the falling edge of SCK. For n-channel open-drain outputs only: External SO resistance: 1 k, external capacitance: 50 pF. Figure 5 Figure 6 Tcyc = 4 x the system clock period For n-channel open-drain outputs only: External resistance: 1 k, external capacitance: 50 pF PE0 64 x TCYC 32 x TCYC 10% 32 x TCYC 10% 1.0 s SI SI 0.5 0.5 s s tCKCY (1) tCKCY (2) tCKL (1) tCKL (2) tCKH (1) tCKH (2) Figure 5 Figure 5 Figure 5 Figure 5 Figure 5 Figure 5 SCK SCK SCK SCK SCK SCK 2.0 32 x TCYC 2.0 32 x TCYC 6.0 64 x TCYC *6 s s s s s s Symbol Conditions Applicable pins/notes Ratings min typ max Unit
Pulse output period
tPCY
s
High-level pulse width
tPH
PE0
s
Low-level pulse width
tPL
PE0
s
Continued on next page.
No. 5190-28/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Parameter Symbol CW Guaranteed constants *7 RW Rl Watchdog timer Clear time (discharge) tWCT Clear period (charge) tWCCY CW Guaranteed constants *7 RW Rl Clear time (discharge) tWCT Clear period (charge) tWCCY Conditions When PE1 has open-drain output specifications When PE1 has open-drain output specifications When PE1 has open-drain output specifications See Figure 7. See Figure 7. When PE1 has open-drain output specifications When PE1 has open-drain output specifications When PE1 has open-drain output specifications See Figure 7. See Figure 7. 2.5 to 5.5 Applicable pins/notes WDR WDR 2.5 to 5.5 WDR WDR WDR WDR WDR WDR WDR WDR 40 12 100 26 0.0475% 6801% 1001% 1001% s ms F k s ms Ratings min typ 0.15% 6801% max Unit F k
VDD (v)
Note: 1. When driven internally using the oscillator circuit shown in Figure 2 with guaranteed constants, values up to the amplitude of the generated oscillation are allowed. 2. The average over a 100-ms period 3. The operating power-supply voltage VDD must be maintained from the point where a HALT instruction is executed until the point where the device has fully entered the standby state. Also, applications must be designed so that no chattering (e.g. switch bounce) occurs on the PA3 pin during a HALT instruction execution cycle. 4. When external clock is selected as the oscillator option, the OSC1 pin has Schmitt characteristics. 5. The values shown for fCFOSC are the frequencies for which oscillation is possible. 6. Tcyc = 4 x the system clock period 7. If this device is used in an environment subject to condensation, extra care is required concerning leakage between PE1 and adjacent pins and leakage associated with external capacitors.
No. 5190-29/35
LC651204N/F/L, LC651202N/F/L
Figure 1 External Clock Input Waveform
Figure 2 Ceramic Oscillator Circuit
Figure 3 Oscillator Stabilization Period
No. 5190-30/35
LC651204N/F/L, LC651202N/F/L Table 1: Guaranteed Ceramic Oscillator Constants
4 MHz (Murata Mfg. Co., Ltd.) CSA4.00MGU CST4.0MGWU (built-in capacitor version) C1 C2 R C1 1 MHz (Murata Mfg. Co., Ltd.) CSB1000J C2 R C1 1 MHz (Kyocera Corporation) KBR1000F C2 R C1 800 kHz (Murata Mfg. Co., Ltd.) CSB800J C2 R C1 800 kHz (Kyocera Corporation) KBR800F C2 R 33 pF 10% 33 pF 10% 0 100 pF 10% 100 pF 10% 2.2 k 100 pF 10% 100 pF 10% 0 100 pF 10% 100 pF 10% 2.2 k 220 pF 10% 220 pF 10% 0 Note: When the power supply rise time is zero, the reset time with CRES = 0.1 F will be between 5 and 50 ms. If the power supply rise time is comparatively long, increase the value of CRES so that the reset time is over 5 ms.
Figure 4 Reset Circuit
Figure 5 Serial I/O Timing
With load conditions identical to those shown in Figure 5
Figure 6 Port PE0 Pulse Output Timing
No. 5190-31/35
LC651204N/F/L, LC651202N/F/L
tWCCY: Charge time due to the external components CW, RW, and Rl tWCT: Discharge time due to program processing
Figure 7 Watchdog Timer Waveform
No. 5190-32/35
LC651204N/F/L, LC651202N/F/L LC651204/1202 Instruction Set (by function) Abbreviations
AC: ACt: CF: CTL: DP: E: EXTF: Fn:
Instruction group
Accumulator Accumulator bit t Carry flag Control register Data pointer E register External interrupt request flag Flag bit n
M: Memory ZF : M(DP): Memory addressed by DP ( )[ ] : P(DPL): I/O port specified by DPL : PC: Program counter +: STACK: Stack pointer -: TM: Timer ^: TMF: Timer (internal) interrupt request flag : At, Ha, La: Working registers :
Instruction code Number of bytes Number of cycles
Zero flag Indicates the contents of the item enclosed. Transfer and direction Addition Subtraction Logical AND Logical OR Logical exclusive OR
Modified status flags ZF CF CF ZF ZF ZF ZF CF CF CF *1
Mnemonic D7 D6 D5 D4 CLA ClC STC CMA INC DEC RAL TAE XAE INM DEm SmB bit RMB bit AD Clear AC Clear CF Set CF Complement AC Increment AC Decrement AC Rotate AC left through CF Transfer AC to E Exchange AC with E Increment M Decrement M Set M data bit Reset M data bit Add M to AC 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 D3 D2 D1 D0 0 0 0 1 1 1 0 0 1 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 1 0 1 1 0 1 1 1 0 1 1 1 1 0 1
Operation
Description
Notes
Accumulator manipulation instructions
1 1 1 1 1 1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 1 1 1
Memory manipulation instructions
AC 0 CF 0 CF 1 AC (AC) AC (AC) + 1 AC (AC) - 1 AC0 (CF), ACn+1 (ACn), CF (AC3) E (AC) (AC) (E) M(DP) [M(DP)] + 1 M(DP) [M(DP)] - 1 M(DP, B1 B0) 1 M(DP, B1 B0) 0 AC (AC) + [M(DP)]
Clears AC. Clears CF. Sets CF. Sets AC to the one's Increments AC. Decrements AC. Shifts AC together with CF left.
B1 B0 B1 B0 0 0
Moves the contents of AC to E. Exchanges the contents of AC and E. Increments M(DP). ZF Decrements M(DP). ZF Sets the bit in M(DP) specified by B1B0 to 1. Clears the bit in M(DP) specified by B1B0 to 0. Adds the contents of AC and M(DP) as two's complement quantities and stores the result ZF in AC. Adds the contents of AC, CF, and M(DP) as two's complement quantities and stores the result in AC. Adds 6 to AC. Adds 10 to AC. Takes the logical exclusive OR of AC and M(DP) and stores the result in AC. Takes the logical AND of AC and M(DP) and stores the result in AC. Takes the logical OR of AC and M(DP) and stores the result in AC. Compares the contents of AC and M(DP) and sets or clears CF and ZF accordingly. Magnitude relationship CF ZF [M(DP)] > (AC) 0 0 [M(DP)] = (AC) 1 1 [M(DP)] < (AC) 1 0 ZF ZF ZF ZF
CF CF
CF
ADC DAA DAS Arithmetic and comparison instructions EXL
Add M to AC with CF Decimal adjust AC in addition Decimal adjust AC in subtraction Exclusive or M to AC
0 1 1 1
0 1 1 1
1 1 1 1
0 0 0 1
0 0 1 0
0 1 0 1
0 1 1 0
0 0 0 1
1 1 1 1
1 1 1 1
AC (AC) + [M(DP)] + (CF) AC (AC) + 3 AC (AC) + 10 AC (AC) [M(DP)] AC (AC) ^ [M(DP)] AC (AC) [M(DP)]
CF
AND OR
And M to AC Or M to AC
1 1
1 1
1 1
0 0
0 0
1 1
1 0
1 1
1 1
1 1
ZF ZF
CM
Compare AC with M
1
1
1
1
1
0
1
1
1
1
[M(DP)] + (AC) + 1
ZF
CF
Cl data
Compare AC with immediate data
0 0
0 1
1 0
0 0
1 I3
1 I2
0 I1
0 I0
2
2
I3 I2 I1 I0 + (AC) + 1
Compares the contents of AC and the immediate data I3 I2 I1 I0 and sets or clears CF and ZF accordingly. Magnitude relationship CF ZF ZF I3 I2 I1 I0 > (AC) 0 0 I3 I2 I1 I0 = (AC) 1 1 I3 I2 I1 I0 < (AC) 1 0 Compares the contents of DPL and the immediate data. Loads AC with the immediate data I3 I2 I1 I0. Stores the contents of AC at M(DP). Loads the contents of M(DP) into AC. Exchanges the contents of AC and M(DP). Then, replaces the contents of DPH with (DPH) 0 M2 M1 M0. Exchanges the contents of AC and M(DP). ZF ZF
CF
CLI data LI data S L Load and store instructions XM data
Compare DPL with immediate data Load AC with immediate data Store AC to M Load AC from M Exchange AC with M then modify DPH with immediate data
0 0 1 0 0 1
0 1 1 0 0 0
1 0 0 0 1 1
0 1 0 0 0 0
1 I3 I3 0 0 0
1 I2 I2 0 0
0 I1 I1 1 0
0 I0 I0 0 1
2 1 1 1 1
2 1 1 1 2
(DPL) I3 I2 I1 I0 AC I3 I2 I1 I0 M(DP) (AC) AC [M(DP)] (AC) [M(DP)] DPH (DPH) 0 M2 M1 M0
*1
ZF ZF ZF is set to indicate the result of the (DPH) 0 M2 M1 M0 operation. ZF is set according to the contents of DPH at the point the instruction was executed. ZF is set to indicate the result of the DPL +1 operation. ZF is set to indicate the result of the DPL -1 operation.
M 2 M1 M0
X
Exchange AC with M
1
0
1
0
0
0
0
0
1
2
(AC) [M(DP)]
ZF
XI
Exchange AC with M then increment DPL Exchange AC with M then Decrement DPL Read table data from program ROM
1
1
1
1
1
1
1
0
1
2
(AC) [M(DP)] DPL (DPL) + 1 (AC) [M(DP)] DPL (DPL) - 1 AC, E ROM (PCh, E, AC)
XD
1
1
1
1
1
1
1
1
1
2
RTBl
0
1
1
0
0
0
1
1
1
2
Exchanges the contents of AC and M(DP). Then, increments ZF the contents of DPL. Exchanges the contents of AC and M(DP). Then, Decrements ZF the contents of DPL. Loads into AC and E the ROM data stored at the location given by the lower 8 bits of the PC, E and AC.
Continued on next page. No. 5190-33/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Number of bytes Number of cycles Instruction group Instruction code Mnemonic D7 D6 D5 D4 LDZ data LHI data IND DED TAL TLA XAH XAt XA0 XA1 XA2 XA3 XHa XH0 XH1 XLa XL0 XL1 SFB flag
Memory manipulation instructions
Modified Operation Description status flags DPH 0 DPL I3 I2 I1 I0 DPH I3 I2 I1 I0 DPL (DPL) + 1 DPL (DPL) - 1 DPL (AC) AC (DPL) (AC) (DPH) (AC) (A0) (AC) (A1) (AC) (A2) (AC) (A3) (DPH) (H0) (DPH) (H1) (DPL) (L0) (DPL) (L1) Fn 1 Loads 0 into DPH and the immediate data I3I2I1I0 into DPL. Loads the immediate data I3 I2 I1 I0 into DPH. Increments the contents of DPL. ZF Decrements the contents of DPL. ZF Moves the contents of AC to DPL. Moves the contents of DPL to AC. ZF Exchanges the contents of AC and DPH. Exchanges the contents of AC and the working register A0, A1, A2, or A3 specified by t1t0. Notes
D3 D2 D1 D0 I3 I3 1 1 0 1 0 t1 0 0 1 1 1 1 1 1 I2 I2 1 1 1 0 0 t0 0 1 0 1 a 0 1 a 0 1 I1 I1 1 1 1 0 1 I0 I0 0 1 1 1 1
Data pointer manipulation instructions
Load DPH with Zero and DPL with immediate data respectively Load DPH with immediate data Increment DPL Decrement DPL Transfer AC to DPL Transfer DPL to AC Exchange AC with DPH
1 0 1 1 1 1 0
0 1 1 1 1 1 0
0 0 1 1 1 1 1
0 0 0 0 1 0 0
1 1 1 1 1 1 1
1 1 1 1 1 1 1
Working register manipulation instructions
Exchange AC with working register At
1 1 1 1 1 1 1 1 0
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 0
0 0 0 0 1 1 1 1 1
0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1
Exchange DPH with working register Ha Exchange DPH with working register Ha Set flag bit
B3 B2 B1 B0
Exchanges the contents of DPH and the working register H0 or H1 specified by a. Exchanges the contents of DPL and the working register L0 or L1 specified by a. Sets the flag specified by B3 B2 B1 B0 to 1. Clears the flag specified by B3 B2 B1 B0 to 0. ZF
RFB flag
Reset flag bit
0
0
0
1
B3 B2 B1 B0
1
1
Fn 0
The flags are divided into four groups, F0 to F3, F4 to F7, F8 to F11, and F12 to F15. ZF is set or cleared according to the 4 bits included in the specified flags.
JMP addr Jump and subroutine instructions
Jumping in the current bank Jumping current page modified by E and AC Call subroutine in the zero page Call subroutine Return from subroutine Return from interrupt routine
0
1
1
0
1 P10 P9 P8 P3 P2 P1 P0 1 0 1 0
2
2
P7 P6 P5 P4 JPEA 1 1 1 1
PC P10 P9 P8 P7 P6 Jumps to the location specified P5 P4 P3 P2 P1 P0 by the immediate data P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0. PC0 to 7 (E, AC) STACK (PC) + 1 PC10 to 6 , PC1 to 0 0 PC5 to 2 P3 P2 P1 P0 STACK (PC) + 2 PC (STACK) PC (STACK) CF, ZF CSF, ZSF Jumps to the location given by replacing the lower 8 bits of the PC with E and AC. Calls a subroutine on page 0. Calls a subroutine. Returns from a subroutine. Returns from an interrupt handling routine. Specifies a pseudo I/O port and changes the bank.
1
1
CZP addr CAL addr RT RTI
1 1 0 0
0 0 1 0
1 1 1 1
1 0 0 0
P3 P2 P1 P0 1 P10 P9 P8 0010 0 0 1 0
1 2 1 1
1 2 1 1
ZF
CF Only valid for the immediately following JMP, I/O, or branch instruction. The mnemonics are BA0 to BA3, reflecting the value of t. The mnemonics are BNA0 to BNA3, reflecting the value of t. The mnemonics are BM0 to BM3, reflecting the value of t. The mnemonics are BNM0 to BNM3, reflecting the value of t. The mnemonics are BP0 to BP3, reflecting the value of t. The mnemonics are BNP0 to BNP3, reflecting the value of t.
BANK
Change bank
1
1
1
1
1
1
0
1
1
1 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if ACt = 1 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if ACt = 0 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if [M(DP, t1 t0)] = 1 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if [M(DP, t1 t0)] = 0 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if [P(DPL, t1 t0)] = 1 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if [P(DPL, t1 t0)] = 0 PC7 to 0 P7 P6 P5 P4 P3 P2 P1 P0 if TMF = 0 then TMF 0 Branches to the location on the same page specified by P7 to P0 if the bit in AC specified by the immediate data t1t0 is 1. Branches to the location on the same page specified by P7 to P0 if the bit in AC specified by the immediate data t1t0 is 0. Branches to the location on the same page specified by P7 to P0 if the bit in M(DP) specified by the immediate data t1 t0 is 1. Branches to the location on the same page specified by P7 to P0 if the bit in M(DP) specified by the immediate data t1 t0 is 0. Branches to the location on the same page specified by P7 to P0 if the bit in port P(DPL) specified by the immediate data t1 t0 is 1. Branches to the location on the same page specified by P7 to P0 if the bit in port P(DPL) specified by the immediate data t1 t0 is 0. Branches to the location on the same page specified by P7 to P0 TMF if TMF is 1. Also clears TMF.
BAt addr
Change bank
0111 P7 P6 P5 P4
0 0 t1 t0 P3 P2 P1 P0
2
2
BNAt addr
Branch on no AC bit
0011 P7 P6 P5 P4
0 0 t1 t0 P3 P2 P1 P0
2
2
BMt addr Branch instructions
Branch on M bit
0111 P7 P6 P5 P4
0 1 t1 t0 P3 P2 P1 P0
2
2
BNMt addr
Branch on no M bit
0011 P7 P6 P5 P4
0 1 t1 t0 P3 P2 P1 P0
2
2
BPt addr
Branch on Port bit
0111 P7 P6 P5 P4
1 0 t1 t0 P3 P2 P1 P0
2
2
BNPt addr
Branch on no Port bit
0011 P7 P6 P5 P4 0111 P7 P6 P5 P4
1 0 t1 t0 P3 P2 P1 P0 1000 P3 P2 P1 P0
2
2
BTM addr
Branch on timer
2
2
Continued on next page.
No. 5190-34/35
LC651204N/F/L, LC651202N/F/L
Continued from preceding page.
Number of bytes Number of cycles Instruction group Instruction code Mnemonic D7 D6 D5 D4 0011 P7 P6 P5 P4 D3 D2 D1 D0 1100 P3 P2 P1 P0 Modified Operation Description status flags PC7 to 0 P7 P6 P5 P4 P7 P6 P5 P4 if TMF = 0 then TMF 0 PC7 to 0 P7 P6 P5 P4 P7 P6 P5 P4 if EXTF = 1 then EXTF 0 PC7 to 0 P7 P6 P5 P4 P7 P6 P5 P4 if EXTF = 0 then EXTF 0 PC7 to 0 P7 P6 P5 P4 P7 P6 P5 P4 if EXTF = 0 PC7 to 0 P7 P6 P5 P4 P7 P6 P5 P4 if CF = 0 PC7 to 0 P7 P6 P5 P4 P7 P6 P5 P4 if ZF = 1 PC7 to 0 P7 P6 P5 P4 P7 P6 P5 P4 if ZF = 0 PC7 to 0 P7 P6 P5 P4 P7 P6 P5 P4 if Fn = 1 Branches to the location on the same page specified by P7 to P0 TMF if TMF is 0. Also clears TMF. Branches to the location on the same page specified by P7 to P0 if EXTF is 1. Also clears EXTF. EXTF Branches to the location on the same page specified by P7 to P0 if EXTF is 0. Also clears EXTF. EXTF Notes
BNTM addr
Branch on no timer
2
2
BI addr
Branch on interrupt
0111 P7 P6 P5 P4
1101 P3 P2 P1 P0
2
2
BNI addr
Branch on no interrupt
0011 P7 P6 P5 P4 0111 P7 P6 P5 P4 0011 P7 P6 P5 P4 0111 P7 P6 P5 P4 0011 P7 P6 P5 P4 1101 P7 P6 P5 P4
1101 P3 P2 P1 P0 1111 P3 P2 P1 P0 1111 P3 P2 P1 P0 1110 P3 P2 P1 P0 1110 P3 P2 P1 P0 n3 n 2 n 1 n 0 P3 P2 P1 P0
2
2
BC addr
Branch on CF
2
2
BNC addr
Branch on no CF
2
2
BZ addr
Branch on ZF
2
2
BNZ addr
Branch on no ZF
2
2
BFn addr
Branch on flag bit
2
2
BNFn addr
Branch on no flag bit
1001 P7 P6 P5 P4 0 0 0 1 0 1 0 0
n3 n 2 n 1 n 0 P3 P2 P1 P0 1 0 1 0 0 0 0 1
2
2
IP I/O instructions OP
Input port to AC Output port to AC
1 1
1 1
SPB bit
Set port bit
0
0
0
0
0
1
B1 B0
1
2
Branches to the location on the same page specified by P7 to P0 if CF is 1. Branches to the location on the same page specified by P7 to P0 if CF is 0. Branches to the location on the same page specified by P7 to P0 if ZF is 1. Branches to the location on the same page specified by P7 to P0 if ZF is 0. Branches to the location on the same page specified by P7 to P0 if the bit in the 16 flags specified by n3 n2 n1 n0 is 1. Branches to the location on the PC7 to 0 P7 P6 P5 P4 same page specified by P to P 7 0 P7 P6 P5 P4 if the bit in the 16 flags specified if Fn = 0 by n3 n2 n1 n0 iis 0. Inputs the contents of port ZF AC [P(DPL)] P(DPL) to AC. Outputs the contents of AC to P(DPL, B1 B0) (AC) port P(DP ). L Sets to 1 the bit in port P(DPL) specified by the immediate data P(DPL, B1 B0) 1 B1 B0. Clears to 0 the bit in port P(DPL) specified by the immediate data B1 B0.
Branch instructions
The mnemonics are BF0 to BF15, reflecting the value of n. The mnemonics are BFN0 to BFN15, reflecting the value of n.
Executing this instruction destroys the contents of the E register. Executing this instruction destroys the contents of the E register.
RPB bit
Reset port bit
0
0
1
0
0
1
B1 B0
1
2
P(DPL, B1 B0) 1 CTL (CTL) B3 B2 B1 B0 CTL (CTL) B3 B2 B1 B0 TM (E), (AC) TMF 0 Halt
ZF
SCTL bit Other instructions
Set control register bit (S) Reset control register bit (S) Write timer
0 0 1 1
0 0 0 1
1 1 0 1
0 0 1 1
1
1
0
0
2
2
RCTL bit WTTM
1100 B3 B2 B1 B0 1 0 1 1
2 1
2 1
Sets the bit (or bits) in the control register specified by B3 B2 B1 B0. Clears the bit (or bits) in the control register specified by B3 ZF B2 B1 B0. Loads the contents of E and AC into the timer. Also clears TMF. TMF Stops all operations.
HALT
Halt
1
1
1
1
0
1
1
0
1
1
This instruction is disabled only when all bits in port PA are 0.
NOP
No operation
0
0
0
0
0
0
0
0
1
1
No operation
Consumes one machine cycle while performing no operation.
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of November, 1997. Specifications and information herein are subject to change without notice. No. 5190-35/35

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